短期課程：The Good, The Bad and The Ugly of Clock Tree Synthesis
舉辦時間：民國106年03月18日 (六) 10:00 - 12:00 (9:40 – 10:00報到)
舉辦地點：元智大學一館 R1309
講員：Cadence (益華電腦) 劉文皓博士
課程大綱：
Clock Synthesis is a mini physical design flow, which includes flip-flop placement, clock wire routing, clock gate insertion, delay calculation, and power/voltage/variation simulation. In order to implement high-performance clock, any clock wire jogging and clock gate displacement matter, which can possibly lead to big skew and slew degradation during clock implementation. However, most existing clock tree studies kind of disconnect to the physical place and route information, and hardly meet the implementation requirement. This talk will introduce the difference between academic and industrial clock synthesis flow, and discuss the emerging issues of high-performance clock implementation.
講員簡歷：
Wen-Hao Liu, received his B.S. and Ph.D. degree in Computer Science from National Chiao Tung University, Taiwan respectively in 2008 and 2013. His research interests include routing, placement, and clock synthesis. Wen-Hao has published 25 papers and 5 patents in these fields, and he has served on the technical program committee of ASPDAC, DAC, and ISPD in the physical design tracks. Currently, Wen-Hao is working at Cadence, Austin, Texas as a Senior Principal Engineer. He co-found a new team in Cadence starting from 3 people to now 30 people, and he is the main developer of the next-generation global routing, clock routing, and Steiner tree generation engines used in Cadence's tools.
指導單位：教育部「產業創新提升人才培育計畫」
承辦單位：元智大學資訊工程學系
聯絡人：陳勇志 03-4638800 ext.3011